Intel 82543GC 사용자 설명서

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Problem:  

Use of the early transmit function may cause hangs in 10/100 Mb/s operation. 

The early transmit feature is only applicable to 10/100 Mbps operation, where it was expected to improve 
overall data transfer rates. With the feature enabled, the 82543GC controller may lock up or exhibit other 
problems; insignificant performance gains were observed. 

Workaround:  

None. Do not use the early transmit function. 

Status:  

Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 
Documentation will change to remove text referring to this feature and its associated registers.  

 

Problem:  

When the TAP controller is inactive, the TDO output remains driven. This behavior does not meet the IEEE 
1149.1 (JTAG) specification.  

The TDO output should float when the TAP controller is not being scanned. The specification requires the ability 
to float the TDO output in order to allow multiple scan chains to be connected in parallel.   

Workaround:  

Do not connect the 82543GC device’s TAP controller in parallel with other JTAG chains. Note that the 82543GC 
device does not support the JTAG scan or bypass instructions. These limitations prevent series connections of 
the TAP controller as well. 

Status:  

Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 

 

Problem:  

When the 82543GC controller powers up, it reads initialization values from EEPROM space. If Initialization 
Control Word 1 bits 15:14 (the signature bits) equal 01b, the controller senses that an EEPROM is present and 
continues processing the initialization values. If the controller detects any other value, it Is supposed to abort 
processing initialization data and use its defaults instead. With this erratum, the controller continues processing 
the EEPROM initialization values even if the signature bits are incorrect.  

This operation could lead to improper initialization from a corrupt EEPROM or from a non-existant EEPROM. 
Note that Erratum #26 also  

Workaround:  

Ensure that an EEPROM is always present and that the signature bits are correct. EEPROMs should also 
always be present to work around Erratum #5, “DAC Accesses May Be Interpreted Incorrectly”. 

Status:  

Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 

 

Problem:  

Link must be present for internal loopback, and loopback operation varies among MII, GMII and TBI modes. 
Loopback cannot be entered directly from 10 Mb/s operation because the loopback data is sampled by 100 
Mb/s clocks.  

Internal loopback testing may be impractical when a real link partner is not present or when a cable is not 
present. Extra software coding may be required to develop satisfactory test routines.  

Workaround:  

The internal loopback path is the same for all modes, but the link requirements differ. In all cases the controller 
must sense that link is up prior to entering loopback. To enter loopback from 100 Mb/s operation when an active 
link partner is not present, toggle the ILOS (Invert Loss of Signal) bit in the Device Control Register to “trick” the 
controller into sensing link is up. For GMII mode (1000 Mb/s), force link if a working gigabit link partner is not 
present. For TBI mode, if a link partner is not present, it is also possible to toggle the ILOS bit to simulate link 
acquisition. In some cases it may be more practical to use external (PHY or transceiver) loopback instead of 
internal loopback. 

Status:  

Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.