Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

A-14

ARM DDI0198D

Table A-7 describes the ARM926EJ-S TCM interface signals.

Output

Data TCM address. This is the word address for the 
access. Valid during request cycles.

Output

Chip select. Indicates if an access will take place in 
the following cycle. Not valid during wait cycles.

Input

Direct memory access address for DTCM memory. If 
DRDMAEN is set to 1, then the value of 
DRDMAADDR is routed directly through to 
DRADDR.

Input

DMA access cycle.
If asserted, DRADDR is directly sourced from 
DRDMAADDR, and DRCS is the result of logically 
ORing DRDMACS with the chip select value for the 
current TCM access.

Input

Direct memory access chip-select for DTCM. 

Output

Data TCM interface idle: 
0 = TCM access 
1 = no access will take place in the current cycle or 
TCM disabled.
Not valid for DMA accesses.

Output

Data TCM read not write:
0 = read 
1 = write.
Indicates if the access is a read or write. Valid during 
request cycles.

Input

Data TCM read data.
Valid during non-waited data cycles.

Output

Request sequential.
Valid during request cycles, asserted during wait 
cycles.
Indicates that the address in the current cycle is 
sequential to the address used during the previous 
request cycle.