Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

4-2

ARM DDI0198D

The ARM926EJ-S processor includes: 

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an Instruction Cache (ICache)

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a Data Cache (DCache)

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a write buffer.

The size of the caches can be from 4KB to 128KB, in power of two increments. 

The caches have the following features:

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The caches are virtual index, virtual tag, addressed using the Modified Virtual 
Address (MVA). This enables the avoidance of cache cleaning and/or invalidating 
on context switch.

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The caches are four-way set associative, with a cache line length of eight words 
per line (32 bytes per line), and with two dirty bits in the DCache.

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The DCache supports write-through and write-back (or copyback) cache 
operations, selected by memory region using the C and B bits in the MMU 
translation tables.

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Allocate on read-miss is supported. The caches perform critical-word first cache 
refilling.

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Pseudo-random or round-robin replacement, selectable by the RR bit in CP15 c1.

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Cache lockdown registers enable control over which cache ways are used for 
allocation on a linefill, providing a mechanism for both lockdown and controlling 
cache pollution.

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The DCache stores the Physical Address (PA) tag corresponding to each DCache 
entry in the tag RAM for use during cache line write-backs, in addition to the 
Virtual Address tag stored in the tag RAM. This means that the MMU is not 
involved in DCache write-back operations, removing the possibility of TLB 
misses related to the write-back address.

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The PLD data preload instruction does not cause data cache linefills. It is treated 
as a NOP instruction. 

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Cache maintenance operations to provide efficient invalidation of:

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the entire DCache or ICache

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regions of the DCache or ICache

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regions of virtual memory.

They also provide operations for efficient cleaning and invalidation of:

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the entire DCache

—

regions of the DCache

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regions of virtual memory.