Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several
memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at
the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes
possible.

The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap action for
every master independently.

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some
masters. This mechanism reduces latency at first access of a burst or single transfer as long as the slave is free from any
other master access, but does not provide any benefit as soon as the slave is continuously accessed by more than one
master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or access latency.

This bus granting mechanism sets a different default master for every slave.

At the end of the current access, if no other request is pending, the slave remains connected to its associated default
master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed
default master.

To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration
Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two
fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no
default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default
master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to 

After the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default
Master suits low-power mode.

This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default
master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave
bus bandwidth is widely used by one or more masters.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput
whatever is the number of requesting masters.

After the end of the current access, if no other request is pending, the slave remains connected to the last master that
performed an access request.

This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non
privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for
masters that mainly perform single accesses or short bursts with some Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput
whatever is the number of requesting masters.

After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike
last access master, the fixed master does not change unless the user modifies it by a software action (field
FIXED_DEFMSTR of the related MATRIX_SCFG).