Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트
제품 코드
AT91SAM9N12-EK
505
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.15 DMAC Channel x [x = 0..7] Descriptor Address Register
Name:
DMAC_DSCRx [x = 0..7]
Addresses:
0xFFFFEC44 [0], 0xFFFFEC6C [1], 0xFFFFEC94 [2], 0xFFFFECBC [3], 0xFFFFECE4 [4], 0xFFFFED0C [5],
0xFFFFED34 [6], 0xFFFFED5C [7]
0xFFFFED34 [6], 0xFFFFED5C [7]
Access: Read-write
Reset:
0x00000000
This register can only be written if the WPEN bit is cleared in
• DSCR_IF: Descriptor Interface Selection
• DSCR: Buffer Transfer Descriptor Address
This address is word aligned.
31
30
29
28
27
26
25
24
DSCR
23
22
21
20
19
18
17
16
DSCR
15
14
13
12
11
10
9
8
DSCR
7
6
5
4
3
2
1
0
DSCR
DSCR_IF
Value
Name
Description
00
AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0 (first DMA Master Interface)
01
AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1 (second DMA Master Interface)