Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

583

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

16. Configure the LLI_B(n).DMAC_CFGx memory location for Channel x as follows:

–FIFOCFG defines the watermark of the DMAC channel FIFO.

–SRC_H2SEL is set to true to enable hardware handshaking on the destination.

–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host 

Controller

17. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, 

then program LLI_B(n).DMAC_DSCR with 0.

18. Program the DMAC_CTRLBx register for Channel x with 0. Its content is updated with the LLI Fetch 

operation.

19. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of 

LLI_B(0).

20. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.

4.

Enable DMADONE interrupt in the HSMCI_IER.

5.

Poll CBTC[x] bit in the DMAC_EBCISR.

6.

If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI errors.

7.

Poll FIFOEMPTY field in the HSMCI_SR.

8.

Send The STOP_TRANSMISSION command writing HSMCI_ARG then HSMCI_CMDR.

9.

Wait for XFRDONE in the HSMCI_SR.

One DMA Transfer descriptor is used to perform the HSMCI block transfer, the DMA writes a rounded up value to the
nearest multiple of 4.

1.

Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK.

2.

Set the ROPT field to 1 in the HSMCI_DMA register.

3.

Issue a READ_MULTIPLE_BLOCK command.

4.

Program the DMA controller to use a list of descriptors:

1.

Read the channel register to choose an available (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the 
DMAC_EBCISR.

3.

Program the channel registers in the Memory with the first descriptor. This descriptor will be word oriented. 
This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n.

4.

The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO 
address.

5.

The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.

6.

Configure the fields of LLI_W(n).DMAC_CTRLAx as follows:

–DST_WIDTH is set to WORD.

–SRC_WIDTH is set to WORD.

–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.

–BTSIZE is programmed with CEILING(block_length/4).

7.

Configure the fields of LLI_W(n).DMAC_CTRLBx as follows:

–DST_INCR is set to INCR

–SRC_INCR is set to INCR

–FC field is programmed with peripheral to memory flow control mode.

–SRC_DSCR is set to 0. (descriptor fetch is enabled for the SRC)

–DST_DSCR is set to TRUE. (descriptor fetch is disabled for the DST)

–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is 

able to prefetch data and write HSMCI simultaneously.