Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the
interrupt sources 1 to 31 (except for those programmed in Fast Forcing).

Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of
the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest.

As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the
nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has
been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register)
is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the
interrupt has been taken into account by the software. 

The current priority level is defined as the priority level of the current interrupt. 

If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the
lowest interrupt source number is serviced first.

The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an
interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software
indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The
write of AIC_EOICR is the exit point of the interrupt handling.

The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of
lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the
processor level. 

When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-
asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service
routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an
embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and
the AIC_EOICR is written. 

The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to
having eight priority levels.

The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to
AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value
written into AIC_SVR corresponding to the current interrupt is returned. 

This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as
AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address
0x0000 0018 through the following instruction: 

LDR

PC,[PC,# -&F20]

When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching
the execution on the correct interrupt handler.

This feature is often not used when the application is based on an operating system (either real time or not). Operating
systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the
interrupt.

However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt
vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating
system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer
the execution on a specific very fast handler and not onto the operating system’s general interrupt handler.