Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

685

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The PWM macrocell is primarily composed of a clock generator module and 4 channels. 



Clocked by the system clock, MCK, the clock generator module provides 13 clocks.



Each channel can independently choose one of the clock generator outputs. 



Each channel generates an output waveform with attributes that can be defined independently for each 
channel through the user interface registers.

Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management
Controller (PMC). 

The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for
all channels. Each channel can independently select one of the divided clocks.
The clock generator is divided in three blocks:



a modulo n counter which provides 11 clocks: F

MCK

, F

MCK

/2, F

MCK

/4, F

MCK

/8, F

MCK

/16, F

MCK

/32, F

MCK

/64, F

MCK

/128, 

F

MCK

/256, F

MCK

/512, F

MCK

/1024 



two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and clkB

Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be
divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA
(clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR).

Modulo n counter

MCK

MCK/2
MCK/4

MCK/16
MCK/32
MCK/64

MCK/8

Divider A

clkA

DIVA

PWM_MR

MCK

MCK/128
MCK/256
MCK/512
MCK/1024

PREA

Divider B

clkB

DIVB

PWM_MR

PREB