Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The DMA transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed
without DMA to ensure that the exact number of bytes are received whatever the system bus latency conditions
encountered during the end of buffer transfer period.

In slave mode, the number of characters to receive must be known in order to configure the DMA.

1.

Initialize the DMA (channels, memory pointers, size -2, etc.);

2.

Configure the master mode (DADR, CKDIV, etc.) or slave mode.

3.

Enable the DMA.

4.

(Master Only) Write the START bit in the TWI_CR to start the transfer.

5.

Wait for the DMA BTC flag.

6.

Disable the DMA.

7.

Wait for the RXRDY flag in the TWI_SR.

8.

Set the STOP command in TWI_CR.

9.

Read the penultimate character in TWI_RHR.

10. Wait for the RXRDY flag in the TWI_SR.

11. Read the last character in TWI_RHR.

12. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.

The TWI interface can perform a Quick Command:

1.

Configure the master mode (DADR, CKDIV, etc.).

2.

Write the MREAD bit in the TWI_MMR at the value of the one-bit command to be sent.

3.

Start the transfer by setting the QUICK bit in the TWI_CR.

TXCOMP

TXRDY

Write QUICK command in TWI_CR

TWD

A

S

DADR

R/W

P