Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트
제품 코드
AT91SAM9N12-EK
877
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
42.7.10 Buffer Structure
The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs. Each data read to DMA buffer,
carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register,
the 4 most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or
better checking the DMA buffer integrity.
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs. Each data read to DMA buffer,
carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register,
the 4 most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or
better checking the DMA buffer integrity.
As soon as touchscreen conversions are required, the pen detection function may help the post-processing of the buffer.
To get more details refer to
To get more details refer to
.
42.7.10.1 Classical ADC Channels Only
When no touchscreen conversion is required (i.e. TSMODE = 0 in ADC_TSMR register), the structure of data within the
buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2 registers.
buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2 registers.
If the user sequence is not used (i.e. USEQ is cleared in ADC_MR register) then only the value of ADC_CHSR register
defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR register
and automatically read to the buffer.
defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR register
and automatically read to the buffer.
When the user sequence is configured (i.e. USEQ is set in ADC_MR register) not only does ADC_CHSR register modify
the data structure of the buffer, but ADC_SEQR1, ADC_SEQR2 registers may modify the data structure of the buffer as
well.
the data structure of the buffer, but ADC_SEQR1, ADC_SEQR2 registers may modify the data structure of the buffer as
well.
Figure 42-13. Buffer Structure when TSMODE = 0
Base Address (BA)
BA + 0x02
ADC_CDR6
6
ADC_CDR5
5
ADC_CDR8
8
BA + 0x04
ADC_CDR6
6
ADC_CDR5
5
ADC_CDR8
8
BA + 0x06
BA + 0x08
BA + 0x0A
ADC_CDR6
6
ADC_CDR5
5
ADC_CDR8
8
BA + [(N-1) * 6]
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 1
ADC_EMR(TAG) = 1
trig.event1
ADC_CDR6
0
ADC_CDR5
0
ADC_CDR8
0
ADC_CDR6
0
ADC_CDR5
0
ADC_CDR8
0
ADC_CDR6
0
ADC_CDR5
0
ADC_CDR8
0
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 0
ADC_EMR(TAG) = 0
DMA Buffer
Structure
Structure
DMA Buffer
Structure
Structure
trig.event2
trig.event1
trig.event2
trig.eventN
trig.eventN
DMA Transfer