Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트

934

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

SSC_RFMR

0xF0010014

Read-write

This register can only be written if the WPEN bit is cleared in 

.

0 = Forbidden value (1-bit data length not supported). 
Any other value: The bit stream contains DATLEN + 1 data bits. 

0 = Normal operating mode.

1 = RD is driven by TD, RF is driven by TF and TK drives RK. 

0 = The lowest significant bit of the data register is sampled first in the bit stream.

1 = The most significant bit of the data register is sampled first in the bit stream.

This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).

This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the 
START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Com-
pare 0 or Compare 1 register. 

This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. 

Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods. 

31

30

29

28

27

26

25

24

FSLEN_EXT

–

–

–

FSEDGE

23

22

21

20

19

18

17

16

–

FSOS

FSLEN

15

14

13

12

11

10

9

8

–

–

–

–

DATNB

7

6

5

4

3

2

1

0

MSBF

–

LOOP

DATLEN