Intel E3815 FH8065301567411 데이터 시트

제품 코드

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

Datasheet

Figure 29

DDR3L Clock Cycle Time ....................................................................... 154

Figure 30

DDR3L Skew between System Memory Differential Clock Pairs (CKP/CKN) ... 155

Figure 31

DDR3L CK High Time ............................................................................ 155

Figure 32

DDR3L CK Low Time ............................................................................. 155

Figure 33

DDR3L DQS Falling Edge Output Access Time to CK Rising Edge ................. 155

Figure 34

DDR3L DQS Falling Edge Output Access Time From CK Rising Edge............. 156

Figure 35

DDR3L CK Rising Edge Output Access Time to the 1st DQS Rising Edge ....... 156

Figure 36

VGA_DDCDATA, and VGA_DDCCLK Timing Diagram.................................. 160

Figure 37

Input Glitch Rejection of Low-Power Receivers ......................................... 161

Figure 38

MIPI-CSI-2 Clock Definition ................................................................... 162

Figure 39

MIPI-CSI-2 Data to Clock Timing Definitions ............................................ 163

Figure 40

SD Card Timing Diagram (DDR50).......................................................... 164

Figure 41

SD card Output Timing Diagram (SDR25) ................................................ 165

Figure 42

SD Card Input Timing Diagram (SDR12).................................................. 165

Figure 43

SD Card Input Timing Diagram (Default) ................................................. 166

Figure 44

SD card Output Timing Diagram (Default)................................................ 167

Figure 45

SD Card Input Timing Diagram (High Speed) ........................................... 168

Figure 46

SD card Output Timing Diagram (High Speed).......................................... 168

Figure 47

SDIO Timing Diagram (DDR50) .............................................................. 169

Figure 48

SDIO Output Timing Diagram (SDR25).................................................... 170

Figure 49

SDIO Output Timing Diagram (SDR12).................................................... 170

Figure 50

SDIO Input Timing Diagram (SDR12/25) ................................................. 171

Figure 51

eMMC* Output Timing Diagram (High Speed Mode) .................................. 172

Figure 52

eMMC* DDR Timings............................................................................. 172

Figure 54

eMMC Clock Signal Timing Diagram (HS200 Mode) ................................... 173

Figure 53

eMMC* Input Timing Diagram (High Speed Mode) .................................... 173

Figure 55

eMMC Input Timing Diagram (HS200 Mode)............................................. 174

Figure 56

USB Rise and Fall Times ........................................................................ 178

Figure 57

USB Full Speed Load............................................................................. 179

Figure 58

USB Differential Data Jitter for Low/Full- Speed ........................................ 179

Figure 59

USB Differential-to-EOP Transition Skew and EOP Width for Low/Full-Speed . 179

Figure 60

USB 3.0 Signals AC Specification ............................................................ 180

Figure 61

ULPI Timing Diagram ............................................................................ 181

Figure 62

V/I Curves for HDA_SDO buffers ............................................................ 182

Figure 63

Maximum AC Waveforms for 1.5 V Signaling ............................................ 185

Figure 64

S Slave Port Timings in I

S Mode ......................................................... 187

Figure 65

S Slave Port Timings in PCM Short Frame Mode ..................................... 187

Figure 66

S Slave Port Timings in PCM Long Frame Mode ...................................... 188

Figure 67

PCI Express* Transmitter Eye ................................................................ 190

Figure 68

PCI Express* Receiver Eye .................................................................... 190

Figure 69

SPI NOR timing .................................................................................... 193

Figure 70

SMBus Transaction ............................................................................... 194

Figure 71

SMBus Timeout .................................................................................... 194

Figure 72

Valid Delay from Rising Clock Edge ......................................................... 195

Figure 73

Output Enable Delay ............................................................................. 195

Figure 74

Float Delay.......................................................................................... 196

Figure 75

Setup and Hold Times ........................................................................... 196

Figure 76

Definition of Timing for F/S-Mode Devices on I

C Bus................................ 198

Figure 77

Definition of Timing for High Speed-Mode Devices on I

C Bus..................... 200

Figure 78

UART Timing Diagram........................................................................... 201

Figure 79

JTAG Timing Diagram ........................................................................... 202

Figure 80

TAP Valid Delay Timing Waveform .......................................................... 203