Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2027
17.17.9
PCS_DWORD8 (pcs_dword8)—Offset 20h
Access Method
Default: 000000C4h
9
X
RO
dfx_cri_lcetraindone:
Local Compare Engine Training Done status indicator Indicates
that the Pattern Checker training is completed (either Pattern Buffer or PRBS). The
Pattern Checker is now synchronized to the Pattern Generator.
8
X
RO
dfx_cri_lcetrainactive:
Local Compare Engine Training Active status indicator
Indicates that the Pattern Checker training is in progress (either Pattern Buffer or
PRBS).
7
0h
RW
reserved501:
reserved
6
0h
RW
cri_dfx_patgen2en:
Pattern Generator 2 Enable In a lane with two Tx paths, this
enables the second Pattern Generator. The DFXPATGENEN will enable the first Pattern
Generator. 0 : Disable second Pattern Generator (default) 1 : Enable second Pattern
Generator
5:4
0h
RW
cri_dfx_maxerrcnt_1_0:
Maximum Error Count Selectable maximum value that the
DFXERRCNT can reach before the Local Compare Engine is automatically stopped. 00 :
2^16 (default) 01 : 2^10 10 : 2^8 11 : 2^4
3:0
9h
RW
cri_dfx_prbstraincnt_3_0:
PRBS Training Count The number of consecutive cycles
that the Pattern Checker's PRBS must be error free before it is considered
synchronized. Default is 9.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword8:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0
re
g_p
artial
re
g_s
lu
m
be
r
re
g_tx
2
_
cd
r_o
ve
rr
ide
_2_
0
re
g_c
d
r_o
ve
rr
ide
_2_
0
reg_ebuffmode
re
g
_
us
ed
cl
oc
kc
h
ann
el_
1
_
0
re
g
_
us
ed
cl
oc
kc
h
ann
el_
ov
rr
ide
reg
_
gb
l_o
vrrid
e
re
g_tx1_p
clk
o
n
_
inp2
re
g_tx2_p
clk
o
n
_
inp2
reg_tx2_tx
enable
cr
i_rx
eb_
p
tr_in
it_3_
0
re
g_p
o
wer
fsm_o
vrrid
e
reg
_
sus
p
en
d
re
g
_
pclkc
fgin
p
ut
reg
_
use
q
cl
ock
cr
i_rx
eb
_hiw
ate
r_3_
0
cr
i_
rx
eb
_l
ow
at
er
_
3
_
0
Bit
Range
Default &
Access
Description
31
0h
RW
reg_partial:
Override for i_partial
30
0h
RW
reg_slumber:
Override for i_slumber
29:27
0h
RW
reg_tx2_cdr_override_2_0:
Override for cdr_override strap for second tx2