Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2037
17.17.17 PCS_DWORD16 (pcs_dword16)—Offset 40h
Access Method
Default: 01000001h
20
1h
RW
o_obsselectm1dataup:
N/N+1 M1-M2 Up data control Selects local 'up' data input
signals from M1 (Tx1) or M2 (Tx2 or Rx) to be sent to the obsselectlocalup muxes that
are controlled by bit 6. 0: select M2 (Tx2 or Rx) 1. select M1 (Tx1)
19:18
0h
RW
o_obsselecttom2_1_0:
N/N+1 M2 Output Select This controls which signals are sent
to Tx2. These outputs are not used when M2 is a Receiver. 00: iabut_obsdown 01:
iabut_obsup 10: output of local 'up' select muxes that are controlled by bit 6 11: GND
17:16
0h
RW
o_obsselecttom1_1_0:
N/N+1 M1 Output Select This controls which signals are sent
to Tx1. 00: iabut_obsdown 01: iabut_obsup 10: output of local 'up' select muxes that
are controlled by bit 6 11: GND
15:14
0h
RW
reg_clkbuf_stagger_cnt_1_0:
Counter override value for staggering delay of clock
buffer control signals.
13:8
3h
RW
reserved513:
reserved
7:0
0h
RW
reg_clkbuf_stagger_cnt_9_2:
Counter override value for staggering delay of clock
buffer control signals.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword16:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
sq
ue
lch_s
hunt_o
vrd_e
n
sq
uelch
_
shun
t_cnt_2_0
re
se
rv
ed
520
i_
rx
sq
fs
m_
ti
me
rs
el
i_rxs
q
_asyn
cmode_h
i_rxs
q
uelchstby_h
re
se
rv
ed
519
cri_dfx_e
venoddmask_1_0
re
se
rv
ed
518
cr
i_dfx_lce2pats
rc_1_0
cr
i_dfx_lcepats
rc_1_0
re
se
rv
ed
517
txloadgen_ctr
_
va
l
cri_txhighpowe
re
i_ovr
d
en
cr
i_tx1highpow
erei_ovrdv
al
cr
i_tx2highpow
erei_ovrdv
al
p2_fast
_
exit_en
Bit
Range
Default &
Access
Description
31
0h
RW
squelch_shunt_ovrd_en:
Squelch Shunt Pulse Duration Override Enable Overrides
the hardware default shunt pulse duration value 1: Shunt Pulse Duration Override
Enable 0: Shunt Pulse Duration Override Disable
30:28
0h
RW
squelch_shunt_cnt_2_0:
Squelch Shunt Pulse Duration Override Value 000 = No
shunt pulse generated 001 = 1 susclk cycles ... 111 = 7 susclk cycles
27
0h
RW
reserved520:
reserved
26
0h
RW
i_rxsqfsm_timersel:
Squelch FSM Timer Select 0 - Selects 25Mhz values for squelch
timer and shunt pulse generation . 1 - Selects 100Mhz values for squelch timer and
shunt pulse generation. This register is applicable to synchronous squelch startup
mode.