Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2067
17.19.2
PCS_DWORD1 (pcs_dword1)—Offset 4h
Access Method
Default: 00600060h
5
0h
RW
reg_tx_laneup:
Unused in Tx
4
0h
RW
reg_left_txfifo_rst_master2:
override enable = reg_lanedeskew_strap_ovrd
3
0h
RW
reg_right_txfifo_rst_master2:
override enable = reg_lanedeskew_strap_ovrd
2
0h
RW
reg_plllinksynch_ovrden:
Override enable for reg_plllinsync_ovrd 0 = Use default
delay in hardware 1 = Use reg_plllinksynch_ovrd
1
0h
RW
reg_plllinksynch_ovrd:
override value for plllinksynch
0
0h
RW
reg_tx1_cmmdisparity:
Sets the initial disparity during Compliance Measurement
Mode, used together with pcs_txcompliance pulse. 0 = set negative disparity 1 = set
positive disparity
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword1:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
re
g_txfsm_4us_de
la
y_7_0
re
g_
so
ft
re
se
t_
en
ab
le
cri_rx
eb
_e
iosenable
cri_r
xdigfilts
q
_enable
re
g_txfs
m
_
d
ela
y_o
vr
d
reg_txfsm_4us_de
la
y_11_8
re
g_pclk_r
ate
_1_0
reg_r
ate
_1_0
re
g_
ph
ymode
_2_0
reg
_
m
ode
ov
re
n
re
g
_
da
ta
width
so
ft_r
es
et_n
re
g_d
igin
elb
en
re
g_di
gife
lbe
n
re
g_
str
apg
ro
u
p
_ov
rd
en
reg_y
an
k_time
r_done_b_o
vr
d
reg_y
ank_time
r_don
e_
b_o
vrd_en
Bit
Range
Default &
Access
Description
31:24
0h
RW
reg_txfsm_4us_delay_7_0:
Override counter value for 4 us delay in txfsm lane reset
to txbiasen delay
23
0h
RW
reg_softreset_enable:
When '1' the soft_reset_n bit will contol the lane reset When
'0' the hardware reset will control the lane reset Note for DP: In addition to
soft_reset_n,which will reset both TX0 and TX 1 in the lane, the reg_tx1_soft_reset_n
bit can be used to reset only TX1 in the lane and reg_tx2_soft_reset_n bit can be used
to reset only TX2
22
1h
RW
cri_rxeb_eiosenable:
When 1 enables EIOS based Rx power down