Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2315
18.7.177 USB Power Gating Control (USB_PGC)—Offset 8168h
Access Method
Default: 00000000h
18.7.178 xHCI Aux Clock Control Register (XHCI_AUX_CCR)—Offset
816Ch
Access Method
2
1b
RW
EN_SCH_TXRXB:
Enable Scheduler Active indication for Tx/Rx Bias circuit HS Phy PM
Policy
Power Well:
Core
1
0b
RW
Enable Rx Bias ckt disable (EN_RXB_CD):
When set enables the Rx bias ckt to be
disabled when conditions met (as described by the HS phy PM policy bits)
Power Well:
Core
0
0b
RW
Enable Tx Bias ckt disable (EN_TXB_CD):
When set enables the Tx bias ckt to be
disabled when conditions met (as described by the HS phy PM policy bits)
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
US
B_SRAM_P
G
E
Bit
Range
Default &
Access
Field Name (ID): Description
31:1
00000000h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
0
0b
RW
USB SRAM power gating enable (USB_SRAM_PGE):
When set enables power
gating on USB ports. Usage of this bit is further qualified with xHCI SRAM Dynamic
Power Gating Disable fuse. If the fuse disables dynamic power gating, setting this bit to
1 shall not enable power gating feature. This bit always returns the value that was
written to it irrespective of the setting of xHCI SRAM Dynamic Power Gating Disable
fuse.
Power Well:
Core