Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2456
Datasheet
19.5
USB 3.0 Device PCI Configuration Registers
19.5.1
reg_GEN_REGRW1_type (GEN_REGRW1)—Offset A0h
General Purpose Read Write Register1
Access Method
Default: 00000000h
Table 218.
Summary of USB 3.0 Device PCI Configuration Registers—0/22/0
Offset
Size
Register ID—Description
Default
Value
A0h
4
00000000h
A4h
4
00000000h
A8h
4
00000000h
ACh
4
00000000h
C0h
4
00000000h
Type:
PCI Configuration Register
(Size: 32 bits)
GEN_REGRW1:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Brdg_rst_mux
En_ot
g
_interr
u
pt
fladj_3
0
mhz_reg
co
re_h
ub_p
ort_o
ve
rc
u
rre
nt
GE
N
_
R
E
G
_
R
W
1
otg
_
ph
y_pw
r_off_re
q
u3_pme_
en
u2_pme_
en
core
_pme
_
en
ulpiphy_refclk_disable
ipma_cmn_refclk_disable
hub
_por
t_pe
rm_attach
host
_
p
o
rt
_
p
owe
r_con
trol
xhci_r
ev
is
ion
bus
_
filter
_byp
ass
Re
se
rv
ed
2
Re
se
rv
ed
1
ot
g_ph
y_pw
r_off_v
eto
ot
g_cn
t_pw
r_off_v
eto
Br
d
g
_
rs
t
Re
se
rv
ed
0
pm_power_state_request
Bit
Range
Default &
Access
Description
31
0b
RW
Brdg_rst_mux:
This is a mux the core reset between the normal reset or reset and
with bdg_reset regRW1[3]
30
0b
RW
En_otg_interrupt:
enable the OTG interrupt
29:24
000000b
RW
fladj_30mhz_reg:
HS jitter adjusment
23
0b
RW
core_hub_port_overcurrent:
This is a generic register provided for product specific
behavior
22
0b
RW
GEN_REG_RW1:
This is a generic register provided for product specific behavior
21
0b
RW
otg_phy_pwr_off_req:
Indicates that the PHY power (both core and suspend well)
can be turned off. Valid for D0 and RTD3hot
20
0b
RW
u3_pme_en:
Determines whether USB3 flis PME events are allowed to trigger PME
events to brige/GPIO