Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

2826

Datasheet

reserved

Default: 00000008h

31:27

00h

RO

This 5-bit field indicates the power states in which the function can 

assert the PME#. A value of 0b for any bit indicates that the function is not capable of 

asserting the PME# signal at the same time in that power state. bit 11 X XXX1b: PME# 

can be asserted from D0 bit 12 X XX1Xb: PME# can be asserted from D1. Bridge does 

not support this state. bit 13 X X1XXb: PME# can be asserted from D2. Bridge does not 

support this state. bit 14 X 1XXXb:PME# can be asserted from D3hot bit 15 1 

XXXXb:PME# can be asserted from D3cold. Bridge does not support this state. This field 

is taken from the private configuration space PME_Support XORed with the 

PME_Support strap.

26:19

00h

RO

reserved

18:16

3h

RO

Indicates support for Revision 1.2 of the PCI Power Management 

Specification.

15:8

00h

RO

Points to the next capability structure. This points to NULL

7:0

01h

RO

Indicates this is power management capability.

Memory Mapped I/O Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Re

se

rv

ed

0

PM

ES

TA

TU

S

Re

se

rv

ed

1

PM

E

E

N

A

BL

E

Re

se

rv

ed

2

NO_SOF

T_RESET

Re

se

rv

ed

3

PO

WE

RST

A

TE

31:16

0000h

RO

reserved

15

0h

RW/1C

0 Software clears the bit by writing a 1 to it. 1 This bit is set when the 

PME# signal is asserted independent of the state of the PME Enable bit

14:9

00h

RO

reserved

8

0h

RW

pme enable

7:4

0h

RO

reserved

3

1h

RO

This bit indicates that devices transitioning from D3hot to D0 

because of Powerstate commands do not perform an internal reset.Configuration 

Context is preserved.