Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
298
Datasheet
12.3.14
DCO (DCO)—Offset Fh
DRAM Control Operation
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd_31_
9_PMST
S
WRO
Rsvd_7_
1_PMST
S
DISR
Bit
Range
Default &
Access
Field Name (ID): Description
31:9
0h
RO
Rsvd_31_9_PMSTS:
Reserved
8
0h
RW/P
WRO:
Warm Reset Occurred. Set by the Punit whenever a Reset Warn is received, and
cleared by powergood=0. 0h: No Warm Reset occurred. 1h: Warm Reset occurred. BIOS
Requirement. BIOS can check and clear this bit whenever executing POST code. This
way BIOS knows that if the bit is set, then DISR indicates whether DRAM entered Self-
Refresh.
7:1
0h
RO
Rsvd_7_1_PMSTS:
Reserved
0
0h
RW/P
DISR:
DRAM In Self-Refresh. Set by Dunit hardware after Channel is placed in self
refresh as a result of a Power State or a Reset Warn sequence. Cleared by Dunit
hardware before starting Channel 0 self refresh exit sequence initiated by a power
management exit. Cleared by the BIOS by writing 1 in a warm reset (Reset# asserted
while PWROK is asserted) exit sequence. 0 - DRAM not guaranteed to be in Self-Refresh.
1 - DRAM in Self-Refresh.
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IC
DIO
IC
PMIDIS
PM
ICTL
Rsvd_27
_9_DCO
RE
UTL
O
CK
Rsvd_7
_1_DCO
DRPL
OC
K
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RW
IC:
Dunit Initialization Complete. This bit should be set by BIOS after Dunit
programming is complete and Dunit is ready to accept PMI requests and perform DRAM
maintenance operations.