Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3183

A full Hot Plug Controller is not implemented.

Presence detection occurs when a PCI Express* device is plugged in and power is 
supplied. The physical layer will detect the presence of the device, and the root port will 
set the SLSTS.PDS and SLSTS.PDC bits.

When a device is removed and detected by the physical layer, the root port will clear 
the SLSTS.PDS bit, and set the SLSTS.PDC bit.

Interrupts can be generated by the root port when a hot plug event occurs. A hot plug 
event is defined as the transition of the SLSTS.PDC bit from 0 to 1. Software can set 
the SLCTL.PDE and SLTCTL.HPE bits to allow hot plug events to generate an interrupt.

If SLCTL.PDE and SLTCTL.HPE are both set, and STSTS.PDC transitions from 0 to 1, an 
interrupt will be generated.

System Error events are support by both internal and external sources. See the PCI 
Express* Base Specification, Rev. 2.0 for details.

Each root port’s link supports L0s, L1, and L2/3 link states per PCI Express* Base 
Specification, Rev. 2.0. L2/3 is entered on entry to S3.

PCI Express* Base Specification, Rev. 2.0

Each root port supports its own extended PCI bridge header in PCI configuration space. 
These headers are located on PCI bus 0, device 28, functions 0-3 as shown below. 
There are no other registers implemented by the root ports or their controller.

See Chapters 

 for additional information.