Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
3890
Datasheet
26.9.1
I2C Control Register (IC_CON)—Offset 0h
This register can be written only when the DW_apb_i2c is disabled, which corresponds
to the IC_ENABLE register being set to 0. Writes at other times have no effect.
Access Method
Default: 0000007Fh
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:24, F:2] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
R
es
er
ve
d
_7
_31
IC_SLA
VE
_DISABLE
IC
_RE
S
TA
R
T
_EN
IC_10
B
IT
A
DDR_MAST
E
R_rd_only
IC_10BIT
ADDR_SLA
VE
SP
EE
D
MASTE
R
_M
ODE
Bit
Range
Default &
Access
Field Name (ID): Description
31:7
0b
RW
Reserved_7_31:
Reserved.
6
1h
RW
IC_SLAVE_DISABLE:
This bit controls whether I2C has its slave disabled. By default,
the slave is always enabled (in reset state as well). If you need to disable it after reset,
set this bit to 1. If this bit is set (slave is disabled), DW_apb_i2c functions only as a
master and does not perform any action that requires a slave.
5
1h
RW
IC_RESTART_EN:
Determines whether RESTART conditions may be sent when acting
as a master. When the RESTART is disabled, the DW_apb_i2c master is incapable of
performing the following functions:
•
•
Sending a START BYTE
•
Performing any high-speed mode operation
•
Performing direction changes in combined format mode
•
Performing a read operation with a 10-bit address
4
1h
RO
IC_10BITADDR_MASTER (IC_10BITADDR_MASTER_rd_only):
Controls whether
the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a
master. If I2C_DYNAMIC_TAR_UPDATE = 1, then this bit is read-only copy of bit 12 of
IC_TAR register.
3
1h
RW
IC_10BITADDR_SLAVE:
When acting as a slave, this bit controls whether the
DW_apb_i2c responds to 7- or 10-bit addresses.
2:1
3h
RW
SPEED:
These bits control at which speed the DW_apb_i2c operates; its setting is
relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects
against illegal values being programmed by software. This register should be
programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise,
hardware updates this register with the value of IC_MAX_SPEED_MODE.
0
1h
RW
MASTER MODE (MASTER_MODE):
This bit controls whether the DW_apb_i2c master
is enabled. Software should ensure that if this bit is set to X, then bit 6 should also be
set to X.