Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4027

Default: 00000000h

7:3

00h

RO

Reserved.

2

0h

RW

If this bit is 0, Bridge does not generate any new upstream 

transaction on IOSF as a master.

1

0h

RW

This bit controls Bridge's response to downstream 

Memory accesses. When set, accesses to memory space of the device is enabled.

0

0h

RO

Reserved.

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLAS

S

_

CO

D

E

S

RID

31:8

000000h

RO

The Class Code register is read-only and used to 

identify the generic function of the device and, in some cases, a specific register level 

programming interface. The register is broken into three byte size fields. The upper byte 

(at offset 0Bh) is a base class code which broadly classifies the type of function the 

device performs. The middle byte (at offset 0Ah) is a sub-class code which identifies 

more specifically the function of the device. The lower byte (at offset 09h) identifies a 

specific register-level programming interface (if any) so that device independent 

software can interact with the device. This register is tied to a strap at the top level.

7:0

00h

RO

Revision ID identifies the revision of particular AHB device. This is 

tied to a strap at the top level.