Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4179
27.5.2
Status and Command (STATUSCOMMAND)—Offset 4h
Access Method
Default: 00100000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re
se
rv
ed
0
SS
E
RMA
RT
A
ST
A
Re
se
rv
ed
1
CA
PLIST
INTR_ST
A
TUS
Re
se
rv
ed
2
Re
se
rv
ed
3
INTR_DIS
ABLE
Re
se
rv
ed
4
SE
RR_ENABLE
Re
se
rv
ed
5
BM
E
MSE
Re
se
rv
ed
6
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RO
Reserved0:
Reserved.
30
0h
RW/1C
SSE:
Reserved.
29
0h
RW/1C
Received Master Abort (RMA):
If the completion status received from IOSF is UR,
Bridge sets this bit. S/W writes a 1. to this bit to clear it. This bit will not be set for the
Fabric port. This bit is not used for the Fabric Port.
28
0h
RW/1C
Received Target Abort (RTA):
If the completion status received from IOSF is CA,
Bridge sets this bit. S/W writes a 1.1 to this bit to clear it. This bit will not be set for the
fabric port. This bit is not used for the Fabric Port.
27
0h
RW/1C
STA:
Reserved.
26:21
00h
RO
Reserved1:
Reserved.
20
1h
RO
Capabilities List (CAPLIST):
Hardwired to 1. Indicates that the controller contains a
capabilities pointer list. The first item is pointed to by looking at configuration offset
34h. If PM capability is not required, then this bit should be tied to 0.
19
0h
RO
Interrupt Status (INTR_STATUS):
This bit reflects state of interrupt in the device.
Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt
Status bit is a 1, will the device.s/function.s INTx# signal be asserted. Setting the
Interrupt Disable bit to a 1 has no effect on the state of this bit. This bit reflects Legacy
interrupt status.
18:16
0h
RO
Reserved2:
Reserved.
15:11
00h
RO
Reserved3:
Reserved.
10
0h
RW
Interrupt Disable (INTR_DISABLE):
Setting this bit disables INTx assertion from
Bridge. The interrupt disabled is legacy INTx# interrupt, i.e. Bridge does not send
Interrupt Assert message through the IOSF SideBand Channel.
9
0h
RO
Reserved4:
Reserved.
8
0h
RW
SERR# Enable (SERR_ENABLE):
If both SERR# Enable and the Unsupported Request
Reporting Enable(URRE) register are 1., the agent sets the Signaled System Error bit in
the PCI Status Register and sends an ERR_NONFATAL message on the IOSF sideband
interface.