Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

4300

Datasheet

I

VRTC

Core Power OK: When asserted, this signal is an 
indication to the SoC that all of its core power rails have 
been stable for 10 ms. It can be driven asynchronously. 
When it is negated, the SoC asserts PMC_PLTRST#.
NOTE: It is required that the power rails associated with 

PCI Express (typically the 3.3V, 5V, and 12V core 
well rails) have been valid for 99 ms prior to 
PMC_CORE_PWROK assertion in order to comply 
with the 100 ms T

PVPERL 

PCI Express 2.0 

specification on PMC_PLTRST# deassertion.

NOTE: PMC_CORE_PWROK must not glitch, even if 

PMC_RSMRST# is low.

O

V1P8A

Platform Reset: The SoC asserts this signal to reset 
devices on the platform. The SoC asserts the signal 
during power-up and when software initiates a reset 
sequence through the Reset Control (RST_CNT) register 
when RST_CNT.sys_rst=1b.

I

V1P8A

Power Button: The signal will cause SCI to indicate a 
system request to go to a sleep state. If the system is 
already in a sleep state, this signal will cause a wake 
event. If the signal is pressed for more than 4 seconds, 
this will cause an unconditional transition (power button 
override) to the S5 state. Override will occur even if the 
system is in the S3 & S4 states. This signal has an 
internal pull-up resistor and has an internal ~16 ms de-
bounce on the input.

I

VRTC

Resume Well Reset: Used for resetting the resume 
well. An external RC circuit is required to guarantee that 
the resume well power is valid prior to this signal going 
high.

I

V1P8S

System Reset: This signal forces an internal reset after 
being debounced (~16 ms).

O

V1P8A

S3 Sleep Control: This signal is for power plane 
control. It can be used to control system power when it 
is in a S3 (Suspend To RAM), S4 (Suspend to Disk), or 
S5 (Soft Off) states.

O

V1P8A

S4 Sleep Control: This signal is for power plane 
control. It can be used to control system power when it 
is in a S4 (Suspend to Disk) or S5 (Soft Off) state.

O

V1P8A

Suspend Status: This signal is asserted by the SoC to 
indicate that the system will be entering a low power 
state soon. This can be monitored by devices with 
memory that need to switch from normal refresh to 
suspend refresh mode. It can also be used by other 
peripherals as an indication that they should isolate 
their outputs that may be going to powered-off planes.
This signal is muxed and may be used by other 
functions.