Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4312
Datasheet
30.6.1
PRSTS - Power and Reset Status (PRSTS)—Offset 0h
Bits in this register only need to be valid for reading when the Main power well is up.
However, since some of the events may initially be detected while the Main power well
is down, they are marked as suspend well bits. All suspend well bits in this register are
reset by global reset#.
Access Method
Default: 00000000h
A8h
4
00000000h
ACh
4
00000000h
B0h
4
00000000h
B4h
4
00000000h
B8h
4
00000000h
BCh
4
00000000h
C0h
4
00000000h
C4h
4
00000000h
C8h
4
00000000h
CCh
4
00000000h
D0h
4
00000000h
D4h
4
00000000h
D8h
4
00000000h
DCh
4
00000000h
Table 293.
Summary of PCU iLB PMC Memory Mapped I/O Registers—
PMC_BASE_ADDRESS (Continued)
Offset
Size
Register ID—Description
Default
Value
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PRSTS:
PMC_BASE_ADDRESS Type:
PCI Configuration Register (Size:
32 bits)
PMC_BASE_ADDRESS Reference:
PMC_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 44h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pmc_pr
odid
pmc_r
evid
pmc_wdt_sts
re
ser
ved
co
de
_co
p
ie
d_sts
re
ser
ved
1
co
de
_load_to
pmc_o
p
_sts
se
c_
gb
lr
st
_
st
s
se
c_wdt_sts
wol_ovr_wk_sts
p
m
c_
host
_
w
ak
e_sts
re
ser
ved
2