Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

4456

Datasheet

7

0b

RW

PEC_EN: When set to '1', this bit causes the host controller to perform the 

SMBus transaction with the Packet Error Checking phase appended. For writes, the 

value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is 

loaded in to the PEC Register. When this bit is cleared to '0', the SMBus host controller 

does not perform the transaction with the PEC phase appended. This bit must be written 

prior to the write in which the START bit is set.

6

0b

WO

START: This write-only bit is used to initiate the command described 

in the SMB_CMD field. All registers should be setup prior to writing a '1' to this bit 

position. This bit always reads zero. The HOST_BUSY bit in the Host Status register 

(offset 00h) can be used to identify when the SMBus controller has finished the 

command.

5

0b

RW

LAST_BYTE: Used for I2C Read commands as an indication that the next byte 

will be the last one to be received for that block. The algorithm and usage model for this 

bit will be as follows (assume a message of n bytes): A. When the software sees the 

BYTE_DONE_STS bit set (bit 7 in the SMBus Host Status Register) for each of bytes 1 

through n-2 of the message, the software should then read the Block Data Byte Register 

to get the byte that was just received. B. After reading each of bytes 1 to n-2 of the 

message, the software will then clear the BYTE_DONE_STS bit. C. After receiving byte 

n-1 of the message, the software will then set the 'LAST BYTE' bit. The software will 

then clear the BYTE_DONE_STS bit. D. The Intel SOC will then receive the last byte of 

the message (byte n). However, the Intel SOC state machine will see the LAST BYTE bit 

set, and instead of sending an ACK after receiving the last byte, it will instead send a 

NAK. E. After receiving the last byte (byte n), the software will still clear the 

BYTE_DONE_STS bit. However, the LAST_BYTE bit will be irrelevant at that point. Note: 

This bit may be set when the TCO timer causes the SECOND_TO_STS bit to be set. See 

the TCO_STS.SECOND_TO_STS register, for more details on that bit. The SMBus device 

driver should clear the LAST_BYTE bit (if it is set) before starting any new command. 

Note: In addition to I2C Read Commands, the LAST_BYTE bit will also cause Block Read/

Write cycles to stop prematurely (at the end of the next byte).