Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
PCU – iLB – Low Pin Count (LPC) Bridge
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4521
The other interrupts decoded via SERIRQ are also ANDed with the corresponding
internal interrupts. For example, if IRQ10 is set to be used as the SCI, then it is ANDed
with the decoded value for IRQ10 from the SERIRQ stream.
internal interrupts. For example, if IRQ10 is set to be used as the SCI, then it is ANDed
with the decoded value for IRQ10 from the SERIRQ stream.
35.3
Use
35.3.1
LPC Clock Delay Compensation
In order to meet LPC interface AC timing requirements, a LPC clock loop back is
required. The operation of this loop back can be configured in two ways:
required. The operation of this loop back can be configured in two ways:
1. On the SOC: In this configuration, ILB_LPC_CLK[0] is looped back on itself on the
SOC pad.
a. Benefit:
ILB_LPC_CLK[0] and ILB_LPC_CLK[1] are both available for system clocking
Table 322. SERIRQ Interrupt Mapping
Data
Frame
#
Interrupt
Clocks
Past Start
Frame
Comment
1
IRQ0
2
Ignored. Can only be generated via the internal 8524
2
IRQ1
5
Before port 60h latch
3
SMI#
8
Causes SMI# if low. Sets SMI_STS.ILB_SMI_STS register
bit.
bit.
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
Ignored. IRQ8# can only be generated internally
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
Before port 60h latch
14
IRQ13
41
Ignored
15
IRQ14
44
Ignored
16
IRQ15
47
17
IOCHCK#
50
Same as ISA IOCHCK# going active.
18
PCI INTA#
53
19
PCI INTB#
56
20
PCI INTC#
59
21
PCI INTD#
62