Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

5057

Access via PCU Proxy, When set to a 1, the corresponding GPIO (if enabled in the 

GPIO_USE_SEL register) if enabled as input via IO_SEL(n), triggered an GPE or SMI. 

This will be set if a 0 to 1 transition occurred and TPE(n) was set, or a 1 to 0 transition 

occurred and TNE(n) was set. If both TPE(n) and TNE(n) are set, then this bit will be 

set on both a 0 to 1 and a 1 to 0 transition. This bit will not be set if the GPIO is 

configured as an output. - Only the 8 lsb are used in VLV

Default: 00000000h

I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:31, F:0] + 48h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

re

se

rv

ed

2

ts

31:12

0h

RO

Reserved.

11:0

0h

WOC

bit 11 - USB_ULPI_0_REFCLK  

bit 10 - USB_ULPI_0_STP  

bit 9 - USB_ULPI_0_NXT  

bit 8 - USB_ULPI_0_DIR  

bit 7 - USB_ULPI_0_DATA7  

bit 6 - USB_ULPI_0_DATA6  

bit 5 - USB_ULPI_0_DATA5  

bit 4 - USB_ULPI_0_DATA4  

bit 3 - USB_ULPI_0_DATA3  

bit 2 - USB_ULPI_0_DATA2  

bit 1 - USB_ULPI_0_DATA1  

bit 0 - USB_ULPI_0_DATA0