Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

5291

The SoC cascades the slave controller onto the master controller through master 
controller interrupt input 2. This means there are only 15 possible interrupts for the 
SoC PIC.

Interrupts can be programmed individually to be edge or level, except for IRQ0, IRQ2 
and IRQ8#.

Active-low interrupt sources (such as a PIRQ#) are inverted inside the SoC. In the 
following descriptions of the 8259s, the interrupt levels are in reference to the signals 
at the internal interface of the 8259s, after the required inversions have occurred. 
Therefore, the term “high” indicates “active,” which means “low” on an originating 
PIRQ#.

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each 
interrupt level. These bits are used to determine the interrupt vector returned, and 
status of any other pending interrupts. 

 defines the IRR, ISR, and IMR.

Master

0

Internal Timer / Counter 0 output or HPET #0; determined by GCFG.LRE 
register bit

1

IRQ1 using SERIRQ, Keyboard Emulation

2

Slave controller INTR output

3

IRQ3 via SERIRQ or PIRQx

4

IRQ4 SERIRQ, PIRQx or PCU UART

5

IRQ5 via SERIRQ or PIRQx

6

IRQ6 via SERIRQ or PIRQx

7

IRQ7 via SERIRQ or PIRQx

Slave

0

Inverted IRQ8# from internal RTC or HPET

1

IRQ9 via SERIRQ, SCI or PIRQx

2

IRQ10 via SERIRQ, SCI or PIRQx

3

IRQ11 via SERIRQ, SCI, HPET or PIRQx

4

IRQ12 via SERIRQ, PIRQx or mouse emulation

5

None

6

PIRQx or IRQ14 from SATA controller

7

IRQ15 via SERIRQ or PIRQx or IRQ15 from SATA controller