Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

5301

Default: 20h

Master Initialization Command Word 3

Default: 00h

Master Operational Control Word 3

7

4

0

0

0

1

0

0

0

0

0

REO

I

OC

W

2

S

ILS

7:5

001b

WO

Rotate and EOI Codes: R, SL, EOI - These three bits control the Rotate and End 

of Interrupt modes and combinations of the two. A chart of these combinations is listed 

above under the bit definition. 000 - Rotate in Auto EOI Mode (Clear) 001 - Non-specific 

EOI command 010 - No Operation 011 - *Specific EOI Command 100 - Rotate in Auto 

EOI Mode (Set) 101 - Rotate on Non-Specific EOI Command 110 - *Set Priority 

Command 111 - *Rotate on Specific EOI Command *L0 - L2 Are Used

4:3

X

WO

OCW2 Select: When selecting OCW2, bits 4:3 = 00

2:0

X

WO

Interrupt Level Select (L2, L1, L0): L2, L1, and L0 determine the interrupt level 

acted upon when the SL bit is active. A simple binary code, outlined above, selects the 

channel for the command to act upon. When the SL bit is inactive, these bits do not 

have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. Bits 

Interrupt Level Bits Interrupt Level 000 IRQ0/8 100 IRQ4/12 001 IRQ1/9 101 IRQ5/13 

010 IRQ2/10 110 IRQ6/14 011 IRQ3/11 111 IRQ7/15

I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

MBZ

CCC

MBZ1

7:3

X

WO

These bits must be programmed to zero.

2

X

WO

Cascaded Controller Connection (CCC): This bit must always be programmed to a 

1 to indicate the slave controller for interrupts 8 15 is cascaded on IRQ2.

1:0

X

WO

These bits must be programmed to zero.

I/O Register

(Size: 8 bits)