Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
5307
42.3.14
SOCW1—Offset ADh
Slave Operational Control Word 1 (Interrupt Mask)
Access Method
Default: 00h
42.3.15
ELCR1—Offset 4D0h
Master Edge/Level Control
Access Method
Default: 00h
7
4
0
0
0
0
0
0
0
0
1
MBZ
SF
NM
BU
F
MSBM
AE
OI
MM
Bit
Range
Default &
Access
Description
7:5
X
WO
MBZ:
These bits must be programmed to zero.
4
0b
WO
SFNM:
Special Fully Nested Mode (SFNM): Should normally be disabled by writing a 0 to
this bit. If SFNM=1, the special fully nested mode is programmed.
3
0b
WO
BUF:
Buffered Mode (BUF): Must be cleared for non-buffered mode. Writing 1 will result
in undefined behavior.
2
0b
WO
MSBM:
Master/Slave in Buffered Mode (MSBM): Not used. Should always be
programmed to 0.
1
0b
WO
AEOI:
Automatic End of Interrupt (AEOI): This bit should normally be programmed to
0. This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt
mode is programmed.
0
1b
WO
MM:
Microprocessor Mode (MM): This bit must be written to 1 to indicate that the
controller is operating in an Intel Architecture-based system. Writing 0 will result in
undefined behavior.
Type:
I/O Register
(Size: 8 bits)
SOCW1:
7
4
0
0
0
0
0
0
0
0
0
IRM
Bit
Range
Default &
Access
Description
7:0
00h
RW
IRM:
Interrupt Request Mask (IRM): When a 1 is written to any bit in this register, the
corresponding IRQ line is masked. When a 0 is written to any bit in this register, the
corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by
the controller. Masking IRQ2 on the master controller will also mask the interrupt
requests from the slave controller.
Type:
I/O Register
(Size: 8 bits)