Texas Instruments TMS320DM644x 사용자 설명서
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2.6
FIFO Operation During Card Read Operation
2.6.1
EDMA Reads
2.6.2
CPU Reads
Peripheral Architecture
The FIFO controller manages the activities of reading the data in from the card and issuing EDMA read
events. Each time an EDMA read event is issued, an EDMA read request interrupt generates.
events. Each time an EDMA read event is issued, an EDMA read request interrupt generates.
provides details of the FIFO controllers operation. As data is received from the card, it is read
into the FIFO. When the number of bytes of data received is equal to the level set by the FIFOLEV bits in
MMCFIFOCTL, an EDMA read event is issued and new EDMA events are disabled until the EDMA is
done with the transfer issued by the current event. Data is read from the FIFO by way of MMCDRR. The
FIFO controller continues to read in data from the card while checking for the EDMA event to occur or for
the FIFO to become full. Once the EDMA event finishes, new EDMA events are enabled. If the FIFO fills
up, the FIFO controller stops the MMC/SD controller from reading any more data until the FIFO is no
longer full.
MMCFIFOCTL, an EDMA read event is issued and new EDMA events are disabled until the EDMA is
done with the transfer issued by the current event. Data is read from the FIFO by way of MMCDRR. The
FIFO controller continues to read in data from the card while checking for the EDMA event to occur or for
the FIFO to become full. Once the EDMA event finishes, new EDMA events are enabled. If the FIFO fills
up, the FIFO controller stops the MMC/SD controller from reading any more data until the FIFO is no
longer full.
An EDMA read event generates when the last data arrives, as determined by the MMC block length
register (MMCBLEN) and the MMC number of blocks register (MMCNBLK) settings. This EDMA event
flushes all of the data that was read from the card from the FIFO.
register (MMCBLEN) and the MMC number of blocks register (MMCNBLK) settings. This EDMA event
flushes all of the data that was read from the card from the FIFO.
Each time an EDMA read event generates, an interrupt (DRRDYINT) generates and the DRRDY bit in the
MMC status register 0 (MMCST0) is also set.
MMC status register 0 (MMCST0) is also set.
The system CPU can also directly read the card data by reading the MMC data receive register
(MMCDRR). The MMC/SD peripheral supports reads that are 1, 2, 3, or 4 bytes wide as, shown in
(MMCDRR). The MMC/SD peripheral supports reads that are 1, 2, 3, or 4 bytes wide as, shown in
and
.
As data is received from the card, it is read into the FIFO. When the number of bytes of data received is
equal to the level set by the FIFOLEV bits in MMCFIFOCTL, a DRRDYINT interrupt is issued and the
DRRDY bit in the MMC status register 0 (MMCST0) is set. Upon receiving the interrupt, the CPU quickly
reads out the bytes received (equal to the level set by the FIFOLEV bits). A DRRDYINT interrupt also
generates when the last data arrives as determined by the MMC block length register (MMCBLEN) and
the MMC numbers of blocks register (MMCNBLK) settings.
equal to the level set by the FIFOLEV bits in MMCFIFOCTL, a DRRDYINT interrupt is issued and the
DRRDY bit in the MMC status register 0 (MMCST0) is set. Upon receiving the interrupt, the CPU quickly
reads out the bytes received (equal to the level set by the FIFOLEV bits). A DRRDYINT interrupt also
generates when the last data arrives as determined by the MMC block length register (MMCBLEN) and
the MMC numbers of blocks register (MMCNBLK) settings.
SPRUE30B – September 2006
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
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