Texas Instruments TMS320DM644x 사용자 설명서
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2.9.3
Initializing the Clock Controller Registers (MMCCLK)
2.9.4
Initialize the Interrupt Mask Register (MMCIM)
2.9.5
Initialize the Time-Out Registers (MMCTOR and MMCTOD)
2.9.6
Initialize the Data Block Registers (MMCBLEN and MMCNBLK)
Peripheral Architecture
A clock divider in the MMC/SD controller divides-down the function clock to produce the memory clock.
Load the divide-down value into the CLKRT bits in the MMC memory clock control register (MMCCLK).
The divide-down value is determined by the following equation:
Load the divide-down value into the CLKRT bits in the MMC memory clock control register (MMCCLK).
The divide-down value is determined by the following equation:
memory clock frequency = function clock frequency/(2 × (CLKRT + 1))
The CLKEN bit in MMCCLK determines whether the memory clock appears on the SD_CLK pin. If you
clear the CLKEN to 0, the memory clock is not provided except when required.
clear the CLKEN to 0, the memory clock is not provided except when required.
The bits in the MMC interrupt mask register (MMCIM) individually enable or disable the interrupt requests.
To enable the associated interrupt request, set the corresponding bit in MMCIM. To disable the associated
interrupt request, clear the corresponding bit. Load zeros into the bits that are not used in the MMC/SD
mode.
To enable the associated interrupt request, set the corresponding bit in MMCIM. To disable the associated
interrupt request, clear the corresponding bit. Load zeros into the bits that are not used in the MMC/SD
mode.
Specify the time-out period for responses using the MMC response time-out register (MMCTOR) and the
time-out period for reading data using the MMC data read time-out register (MMCTOD).
time-out period for reading data using the MMC data read time-out register (MMCTOD).
When the MMC/SD controller sends a command to a memory card, it must often wait for a response. The
MMC/SD controller can wait indefinitely or up to 255 memory clock cycles. If you load 0 into MMCTOR,
the MMC/SD controller waits indefinitely for a response. If you load a nonzero value into MMCTOR, the
MMC/SD controller stops waiting after the specified number of memory clock cycles and then sets a
response time-out flag (TOUTRS) in the MMC status register 0 (MMCST0). If you enable the associated
interrupt request, the MMC/SD controller also sends an interrupt request to the ARM.
MMC/SD controller can wait indefinitely or up to 255 memory clock cycles. If you load 0 into MMCTOR,
the MMC/SD controller waits indefinitely for a response. If you load a nonzero value into MMCTOR, the
MMC/SD controller stops waiting after the specified number of memory clock cycles and then sets a
response time-out flag (TOUTRS) in the MMC status register 0 (MMCST0). If you enable the associated
interrupt request, the MMC/SD controller also sends an interrupt request to the ARM.
When the MMC/SD controller requests data from a memory card, it can wait indefinitely for that data or it
can stop waiting after a programmable number of cycles. If you load 0 into MMCTOD, the MMC/SD
controller waits indefinitely. If you load a nonzero value into MMCTOD, the MMC/SD controller waits the
specified number of memory clock cycles and then sets a read data time-out flag (TOUTRD) in MMCST0.
If you enable the associated interrupt request, the MMC/SD controller also sends an interrupt request to
the ARM.
can stop waiting after a programmable number of cycles. If you load 0 into MMCTOD, the MMC/SD
controller waits indefinitely. If you load a nonzero value into MMCTOD, the MMC/SD controller waits the
specified number of memory clock cycles and then sets a read data time-out flag (TOUTRD) in MMCST0.
If you enable the associated interrupt request, the MMC/SD controller also sends an interrupt request to
the ARM.
Specify the number of bytes in a data block in the MMC block length register (MMCBLEN) and the number
of blocks in a multiple-block transfer in the MMC number of blocks register (MMCNBLK).
of blocks in a multiple-block transfer in the MMC number of blocks register (MMCNBLK).
You must define the size for each block of data transferred between the MMC/SD controller and a memory
card in MMCBLEN. The valid size depends on the type of read/write operations. A length of 0 bytes is
prohibited.
card in MMCBLEN. The valid size depends on the type of read/write operations. A length of 0 bytes is
prohibited.
For multiple-block transfers, you must specify how many blocks of data are to be transferred between the
MMC/SD controller and a memory card. You can specify an infinite number of blocks by loading 0 into
MMCNBLK. When MMCNBLK = 0, the MMC/SD controller continues to transfer data blocks until the
transferring is stopped with a STOP_TRANSMISSION command. To transfer a specific number of blocks,
load MMCNBLK with a value from 1 to 65 535.
MMC/SD controller and a memory card. You can specify an infinite number of blocks by loading 0 into
MMCNBLK. When MMCNBLK = 0, the MMC/SD controller continues to transfer data blocks until the
transferring is stopped with a STOP_TRANSMISSION command. To transfer a specific number of blocks,
load MMCNBLK with a value from 1 to 65 535.
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
24
SPRUE30B – September 2006