Intel 80C196NU 사용자 설명서
8XC196NP, 80C196NU USER’S MANUAL
2-14
•
The 80C196NU’s PWM has an additional prescaler option (divide-by-4), controlled by the
PWM control register (CON_REG0).
PWM control register (CON_REG0).
•
When operating with a demultiplexed bus, the 80C196NU can add an automatic delay in the
first cycle following a chip-select change or in a write cycle that follows a read. This mode,
called deferred mode, extends the following timing specifications by two clock periods (2t):
T
first cycle following a chip-select change or in a write cycle that follows a read. This mode,
called deferred mode, extends the following timing specifications by two clock periods (2t):
T
AVDV
, T
AVWL
, T
AVRL
, T
RLDV
, T
RHDZ
, T
RHRL
, T
LHLH
, T
RHLH
, T
SLDV
, and T
WHLH
.
•
The 80C196NU has an additional power-saving mode, standby (IDLPD #3).
•
The 8XC196NP allows you to change the value of EP_REG to control which memory page
a nonextended instruction accesses. However, software tools require that EP_REG be equal
to 00H. The 80C196NU forces all nonextended data accesses to page 00H. You cannot use
EP_REG to change pages.
a nonextended instruction accesses. However, software tools require that EP_REG be equal
to 00H. The 80C196NU forces all nonextended data accesses to page 00H. You cannot use
EP_REG to change pages.
•
After a HOLD request, the 80C196NU’s chip-select channels become inactive before the
80C196NU asserts HLDA#.
80C196NU asserts HLDA#.
•
In demultiplexed mode, the 80C196NU’s RD# and WR# signals are asserted one clock
period (1t) earlier than on the 80C196NP.
period (1t) earlier than on the 80C196NP.