Hitachi HTS543212L9SA00 Manual Do Utilizador

 

                       5K320 SATA OEM Specification 

 

- 49 - 

This register contains Bits 16-23. At the end of the command, this register is updated to reflect the 
current LBA Bits 16-23.   

When 48 -bit addressing commands are used, the “most recently written” content contains LBA Bits 
16-23, and the “previous content” contains Bits 40-47. The 48-bit Address feature set is described in 
“12.14 48-bit Address Feature Set”.   

 

This register contains Bits 0-7. At the end of the command, this register is updated to reflect the 
current LBA Bits 0-7.   

When 48-bit commands are used, the “most recently written” content contains LBA Bits 0-7, and the 
“previous content” contains Bits 24-31.   

 

This register contains Bits 8 -15. At the end of the command, this register is updated to reflect the 
current LBA Bits 8-15.   

When 48 -bit addressing commands are used, the “most recently written” content contains LBA Bits 
8-15, and the “previous content” contains Bits 32-39.   

 

This register contains the number of sectors of data requested to be transferred on a read or write 
operation between the host and the device. If the value in the register is set to 0, a count of 256 
sectors (in 28-bit addressing) or 65,536 sectors (in 48-bit addressing) is specified.   

If the register is zero at command completion, the command was successful. If not successfully 
completed, the register contains the number of sectors which need to be transferred in order to 
complete the request.   

The contents of the register are defined otherwise on some commands. These definitions are given in 
the command descriptions.   

 

Status Register 

7 

6 

5 

4 

3 

2 

1 

0 

B S Y 

DRDY 

DF 

DSC 

DRQ 

CORR 

I D X 

ERR 

Table  28 Status Register   

This register contains the device status. The contents of this register are updated whenever an error 
occurs and at the completion of each command.   

If the host reads this register when an interrupt is pending, it is considered to be the interrupt 
acknowledge. Any pending interrupt is cleared whenever this register is read.   

If BSY=1, no other bits in the register are valid.  

Bit Definitions 

  

BSY 

Busy. BSY=1 whenever the device is accessing the registers. The host should not read or 
write any registers when BSY=1. If the host reads any register when BSY=1, the contents of 
the Status Register will be returned.