Fujitsu MCM3130SS Manual Do Utilizador
SCSI BUS
7-40 C156-E228-02EN
7.7 Bus Conditions
Two types of asynchronous operations, an ATTENTION condition and a RESET
condition, are provided to control and modify the bus phase transition sequence
(bus condition).
condition, are provided to control and modify the bus phase transition sequence
(bus condition).
7.7.1 ATTENTION condition
The ATTENTION condition allows an INIT to report that the INIT has messages
to be sent to the TARG. The TARG receives a message from the INIT by
executing the MESSAGE OUT phase. Figure 7.19 shows the ATTENTION
condition.
to be sent to the TARG. The TARG receives a message from the INIT by
executing the MESSAGE OUT phase. Figure 7.19 shows the ATTENTION
condition.
(1) Generation and release of ATTENTION condition (INIT)
By making the ATN signal true, the INIT can generate the ATTENTION
condition any time except during the ARBITRATION or BUS FREE phase.
condition any time except during the ARBITRATION or BUS FREE phase.
Consider the generation of a new ATTENTION condition in the INFORMATION
TRANSFER phase. To inform the TARG of the ATTENTION condition before
the transition to the next new bus phase, the INIT must set the ATN signal true
before Deskew Delay
TRANSFER phase. To inform the TARG of the ATTENTION condition before
the transition to the next new bus phase, the INIT must set the ATN signal true
before Deskew Delay
×
2 or more from the timing of setting the ACK signal false
for the last byte being transferred in the current bus phase. If the ATN sending
timing is delayed, the TARG may not be informed of the ATTENTION condition
until the next bus phase. The INIT may not operate as it should.
timing is delayed, the TARG may not be informed of the ATTENTION condition
until the next bus phase. The INIT may not operate as it should.
When transferring message information in several bytes in the MESSAGE OUT
phase, the INIT must keep the ATN signal true. The INIT can make the ATN
signal false any time except while the ACK signal is true in the MESSAGE OUT
phase. When transferring the last byte in the MESSAGE OUT phase, the INIT
generally makes the ATN signal false during the period between the time the REQ
signal becomes true and the time it returns the ACK signal. In this case, the INIT
must set the ATN signal false before Deskew Delay
phase, the INIT must keep the ATN signal true. The INIT can make the ATN
signal false any time except while the ACK signal is true in the MESSAGE OUT
phase. When transferring the last byte in the MESSAGE OUT phase, the INIT
generally makes the ATN signal false during the period between the time the REQ
signal becomes true and the time it returns the ACK signal. In this case, the INIT
must set the ATN signal false before Deskew Delay
×
2 or more from the time of
setting the ACK signal true.
The INIT must make the ATN signal false before making the ACK signal true to
transfer the last message byte if so specified for the particular type of message to
the TARG. (See "MCD3130SS, MCE3130SS, MCK3130SS, MCM3064SS,
MCM3130SS Optical Disk Drives SCSI Logical Interface Specifications.")
transfer the last message byte if so specified for the particular type of message to
the TARG. (See "MCD3130SS, MCE3130SS, MCK3130SS, MCM3064SS,
MCM3130SS Optical Disk Drives SCSI Logical Interface Specifications.")