Fujitsu MCE3130AP Manual Do Utilizador
4 - 28
C156-E142-02EN
4.5.3
DEVICE RESET (X'80')
Table 4.22 DEVICE RESET command
Bit
7
6
5
4
3
2
1
0
CM
0
0
0
0
1
0
0
0
DH
X
X
X
DRV
X
X
X
X
CH
X
X
X
X
X
X
X
X
CL
X
X
X
X
X
X
X
X
SN
X
X
X
X
X
X
X
X
SC
X
X
X
X
X
X
X
X
FR
X
X
X
X
X
X
X
X
The DEVICE RESET command resets the ODD.
When the ODD receives the DEVICE RESET command, it sets the BUSY bit to 1. After reset is
completed, the ODD sets the BUSY bit to 0. INTRQ is not asserted.
completed, the ODD sets the BUSY bit to 0. INTRQ is not asserted.
4.5.4
CHECK POWER MODE (X'98'/X'E5')
Table 4.23 CHECK POWER MODE command
Bit
7
6
5
4
3
2
1
0
CM
1
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
DH
X
X
X
DRV
X
X
X
X
CH
X
X
X
X
X
X
X
X
CL
X
X
X
X
X
X
X
X
SN
X
X
X
X
X
X
X
X
SC
X
X
X
X
X
X
X
X
FR
X
X
X
X
X
X
X
X
The CHECK POWER MODE command sets the ODD power mode status in the SC register, then
notifies the host of the value in Table 4.24 When the drive is in sleep mode, the interface is
inactive and the ODD cannot receive this command.
notifies the host of the value in Table 4.24 When the drive is in sleep mode, the interface is
inactive and the ODD cannot receive this command.