Fujitsu MHV2080AT Manual Do Utilizador

 

C141-E218 

5-143 

The following steps shall occur in the order they are listed unless otherwise 
specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 

1)  The host shall keep DMACK- in the negated state before an Ultra DMA burst 

is initiated. 

2)  The device shall assert DMARQ to initiate an Ultra DMA burst. 

3)  Steps (3), (4), and (5) may occur in any order or at the same time.  The host 

shall assert STOP. 

4)  The host shall assert HSTROBE. 

5)  The host shall negate CS0-, CS1-, DA2, DA1, and DA0.  The host shall keep 

CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at 
the end of the burst. 

6)  Steps (3), (4), and (5) shall have occurred at least t

ACK

 before the host asserts 

DMACK-.  The host shall keep DMACK- asserted until the end of an Ultra 
DMA burst. 

7)  The device may negate DDMARDY- t

ZIORDY

 after the host has asserted 

DMACK-.  Once the device has negated DDMARDY-, the device shall not 
release DDMARDY- until after the host has negated DMACK- at the end of 
an Ultra DMA burst. 

8)  The host shall negate STOP within t

ENV

 after asserting DMACK-.  The host 

shall not assert STOP until after the first negation of HSTROBE. 

9)  The device shall assert DDMARDY- within t

LI

 after the host has negated 

STOP.  After asserting DMARQ and DDMARDY- the device shall not 
negate either signal until after the first negation of HSTROBE by the host. 

10)  The host shall drive the first word of the data transfer onto DD (15:0).  This 

step may occur any time during Ultra DMA burst initiation. 

11)  To transfer the first word of data:  the host shall negate HSTROBE no sooner 

than t

LI

 after the device has asserted DDMARDY-.  The host shall negate 

HSTROBE no sooner than t

DVS

 after the driving the first word of data onto DD 

(15:0).