Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

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Port B
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
105
10.3.2  Data Direction Register B 
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 
logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the 
output buffer.
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins 
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before 
changing data direction register B bits from 0 to 1.
 shows the port B I/O logic.
Figure 10-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, 
regardless of the state of its data direction bit. 
 summarizes the operation of the port B pins.
Address:
$0005
Bit  7
6
5
4
3
2
1
Bit  0
Read:
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 10-6. Data Direction Register B (DDRB)
Table 10-2. Port B Pin Functions
DDRB Bit
PTB Bit
I/O Pin Mode
Accesses to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X
(1)
1. X = don’t care
Input, Hi-Z
(2)
2. Hi-Z = high impedance
DDRB[7:0]
Pin
PTB[7:0]
(3)
3. Writing affects data register, but does not affect input.
1
X
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
READ PTB ($0001)
PTBx
DDRBx
PTBx
INTER
NAL DATA BUS