Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador
Input/Output (I/O) Ports (PORTS)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
110
Freescale Semiconductor
10.7 Port F
Port F is a 6-bit, special function port that shares four of its pins with the serial peripheral interface module
(SPI) and two pins with the serial communications interface (SCI).
(SPI) and two pins with the serial communications interface (SCI).
10.7.1 Port F Data Register
The port F data register (PTF) contains a data latch for each of the six port F pins.
PTF[5:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[5:0].
of the corresponding bit in data direction register F. Reset has no effect on PTF[5:0].
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the SPI or SCI module. However, the DDRF bits
always determine whether reading port F returns the states of the latches
or the states of the pins.
pins that are being used by the SPI or SCI module. However, the DDRF bits
always determine whether reading port F returns the states of the latches
or the states of the pins.
10.7.2 Data Direction Register F
Data direction register F (DDRF) determines whether each port F pin is an input or an output. Writing a
logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the
output buffer.
logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the
output buffer.
DDRF[5:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[5:0], configuring all port F pins
as inputs.
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
changing data direction register F bits from 0 to 1.
Address:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
Write:
R
R
Reset:
Unaffected by reset
R
= Reserved
Figure 10-16. Port F Data Register (PTF)
Address:
$000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
Write:
R
R
Read:
0
0
0
0
0
0
R
= Reserved
Figure 10-17. Data Direction Register F (DDRF)