Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador
Control Logic Block
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
153
FFLAG1 — Fault Event Flag 1
The FFLAG1 event bit is set within two CPU cycles after a rising edge on fault pin 1. To clear the
FFLAG1 bit, the user must write a 1 to the FTACK1 bit in the fault acknowledge register.
FFLAG1 bit, the user must write a 1 to the FTACK1 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 1.
0 = No new fault on fault pin 1.
0 = No new fault on fault pin 1.
12.9.10 Fault Acknowledge Register
The fault acknowledge register (FTACK) is used to acknowledge and clear the FFLAGs. In addition, it is
used to monitor the current sensing bits to test proper operation.
used to monitor the current sensing bits to test proper operation.
FTACK4 — Fault Acknowledge 4 Bit
The FTACK4 bit is used to acknowledge and clear FFLAG4. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG4. Writing a 0 will have no effect.
this bit will clear FFLAG4. Writing a 0 will have no effect.
FTACK3 — Fault Acknowledge 3 Bit
The FTACK3 bit is used to acknowledge and clear FFLAG3. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG3. Writing a 0 will have no effect.
this bit will clear FFLAG3. Writing a 0 will have no effect.
FTACK2 — Fault Acknowledge 2 Bit
The FTACK2 bit is used to acknowledge and clear FFLAG2. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG2. Writing a 0 will have no effect.
this bit will clear FFLAG2. Writing a 0 will have no effect.
FTACK1 — Fault Acknowledge 1 Bit
The FTACK1 bit is used to acknowledge and clear FFLAG1. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG1. Writing a 0 will have no effect.
this bit will clear FFLAG1. Writing a 0 will have no effect.
DT6 — Dead-Time 6 Bit
Current sensing pin IS3 is monitored immediately before dead-time ends due to the assertion of
PWM6.
PWM6.
DT5 — Dead-Time 5 Bit
Current sensing pin IS3 is monitored immediately before dead-time ends due to the assertion of
PWM5.
PWM5.
DT4 — Dead-Time 4 Bit
Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of
PWM4.
PWM4.
DT3 — Dead-Time 3 Bit
Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of
PWM3.
PWM3.
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
DT6
DT5
DT4
DT3
DT2
DT1
Write:
FTACK4
FTACK3
FTACK2
FTACK1
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-45. Fault Acknowledge Register (FTACK)