Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

165

During an SCI reception, the receive shift register shifts characters in from the PTF4/RxD pin. The SCI 
data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.

After a complete character shifts into the receive shift register, the data portion of the character transfers 
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that 
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the 
SCRF bit generates a receiver CPU interrupt request.

The receiver samples the PTF4/RxD pin at the RT clock rate. The RT clock is an internal signal with a 
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at 
these times (see 

•

After every start bit

•

After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at 
RT8, RT9, and RT10 return a valid 1 and the majority of the next RT8, RT9, and RT10 samples 
return a valid 0)

 

To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. 
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. 

 summarizes the results of the start bit verification samples.

RT CLOCK

RESET

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

2

RT

3

RT

4

RT

5

RT

8

RT

7

RT

6

RT11

RT10

RT

9

RT15

RT14

RT13

RT12

RT16

RT

1

RT

2

RT

3

RT

4

START BIT

QUALIFICATION

START BIT

VERIFICATION

DATA

SAMPLING

SAMPLES

RT

CLOCK

RT CLOCK

STATE

START BIT

LSB

PTF4/RxD