Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador
Serial Communications Interface Module (SCI)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
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Freescale Semiconductor
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Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
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Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop
bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU
interrupt requests.
bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU
interrupt requests.
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Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
13.4 Wait Mode
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
The SCI module remains active after the execution of a WAIT instruction. In wait mode the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
module before executing the WAIT instruction.
13.5 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
13.6 I/O Signals
Port F shares two of its pins with the SCI module. The two SCI input/output (I/O) pins are:
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PTF5/TxD — Transmit data
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PTF4/RxD — Receive data
13.6.1 PTF5/TxD (Transmit Data)
The PTF5/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTF5/TxD pin
with port F. When the SCI is enabled, the PTF5/TxD pin is an output regardless of the state of the DDRF5
bit in data direction register F (DDRF).
with port F. When the SCI is enabled, the PTF5/TxD pin is an output regardless of the state of the DDRF5
bit in data direction register F (DDRF).