Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

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Freescale Semiconductor

Four SPI status flags can be enabled to generate CPU interrupt requests as shown in 

The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU 
interrupt requests, provided that the SPI is enabled (SPE = 1).

The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt 
requests, provided that the SPI is enabled (SPE = 1). (See 

The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error 
CPU interrupt request. 

The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF 
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.

These sources in the SPI status and control register can generate CPU interrupt requests:

•

SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift 
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, 
SPRF can generate either an SPI receiver/error or CPU interrupt.

•

SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the 
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, 
SPTE can generate either an SPTE or CPU interrupt request.

SPTE transmitter empty

SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1)

SPRF receiver full

SPI receiver CPU interrupt request (SPRIE = 1)

OVRF overflow

SPI receiver/error interrupt request (ERRIE = 1)

MODF mode fault

SPI receiver/error interrupt request (ERRIE = 1)

SPTE

SPTIE

SPRF

SPRIE

ERRIE

MODF

OVRF

SPE

SPI TRANSMITTER

CPU INTERRUPT REQUEST

SPI RECEIVER/ERROR

CPU INTERRUPT REQUEST