Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

212

Freescale Semiconductor

This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See 

. Reset clears the SPE bit.

1 = SPI module enabled
0 = SPI module disabled

SPTIE— SPI Transmit Interrupt Enable Bit

This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte 
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.

1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled

The SPI status and control register (SPSCR) contains flags to signal these conditions:

•

Receive data register full

•

Failure to clear SPRF bit before next byte is received (overflow error)

•

Inconsistent logic level on SS pin (mode fault error)

•

Transmit data register empty

The SPI status and control register also contains bits that perform these functions:

•

Enable error interrupts

•

Enable mode fault error detection

•

Select master SPI baud rate

This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data 
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.

During an SPRF CPU interrupt (DMAS = 0), the CPU clears SPRF by reading the SPI status and 
control register with SPRF set and then reading the SPI data register. 

Reset clears the SPRF bit.

1 = Receive data register full
0 = Receive data register not full

This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears 
the ERRIE bit.

1 = MODF and OVRF can generate CPU interrupt requests.
0 = MODF and OVRF cannot generate CPU interrupt requests.

Address: $0045

Bit  7

6

5

4

3

2

1

Bit  0

Read:

SPRF

ERRIE

OVRF

MODF

SPTE

MODFEN

SPR1

SPR0

Write:

R

R

R

R

Reset:

0

0

0

0

1

0

0

0

R

= Reserved