Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

255

The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. 
The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. 

This read/write bit is set when a break interrupt causes an exit from wait mode. Clear BW by writing a 
logic 0 to it. Reset clears BW. 

1 = Break interrupt during wait mode
0 = No break interrupt during wait mode

BW can be read within the break interrupt routine. The user can modify the return address on the stack 
by subtracting 1 from it. 

The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the 
MCU is in a break state.

This read/write bit enables software to clear status bits by accessing status registers while the MCU is 
in a break state. To clear status bits during the break state, the BCFE bit must be set.

1 = Status bits clearable during break
0 = Status bits not clearable during break

The monitor ROM (MON) allows complete testing of the microcontroller unit (MCU) through a single-wire 
interface with a host computer. Monitor mode entry can be achieved without the use of V

TST

 as long as 

vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit 
programming. 

Address:

$FE00

Bit  7

6

5

4

3

2

1

Bit  0

Read:

R

R

R

R

R

R

BW

R

Write:

Reset:

0

Address:

$FE03

Bit  7

6

5

4

3

2

1

Bit  0

Read:

BCFE

R

R

R

R

R

R

R

Write:

Reset:

0

R

=  Reserved