Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

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Analog-to-Digital Converter (ADC)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
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Freescale Semiconductor
3.4  Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC 
conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a 
conversion complete flag when interrupts are enabled.
3.5  Wait Mode
The WAIT instruction can put the MCU in low power-consumption standby mode.
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC 
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power 
down the ADC by setting ADCH[4:0] in the ADC status and control register before executing the WAIT 
instruction.
3.6  I/O Signals
The ADC module has 10 input signals that are shared with port B and port C. 
3.6.1  ADC Analog Power Pin (V
DDAD
The ADC analog portion uses V
DDAD
 as its power pin. Connect the V
DDAD
 pin to the same voltage 
potential as V
DD
. External filtering may be necessary to ensure clean V
DDAD
 for good results.
NOTE
Route V
DDAD
 carefully for maximum noise immunity and place bypass 
capacitors as close as possible to the package.
3.6.2  ADC Analog Ground Pin (V
SSAD
The ADC analog portion uses V
SSAD 
as its ground pin. Connect the V
SSAD
 pin to the same voltage 
potential as V
SS
.
3.6.3  ADC Voltage Reference Pin (V
REFH
)
V
REFH
 is the power supply for setting the reference voltage V
REFH
. Connect the V
REFH
 pin to the same 
voltage potential as 
V
DDAD
. There will be a finite current associated with V
REFH
. See 
NOTE
Route V
REFH
 carefully for maximum noise immunity and place bypass 
capacitors as close as possible to the package.
3.6.4  ADC Voltage Reference Low Pin (V
REFL
)
V
REFL
 is the lower reference supply for the ADC. Connect the V
REFL
 pin to the same voltage potential as 
V
SSAD
. A finite current will be associated with V
REFL
. See 
.
NOTE
In the 56-pin shrink dual in-line package (SDIP), V
REFL
 and V
SSAD
 are tied 
together.