Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

97

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V

DD

 pin 

and can force a reset when the V

DD

 voltage falls to the LVI trip voltage.

Features of the LVI module include:

•

Programmable LVI reset

•

Programmable power consumption

•

Digital filtering of V

DD

 pin level

•

Selectable LVI trip voltage

 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module 

contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to 
monitor V

DD

 voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when V

DD 

falls below a voltage, V

LVRX

, and remains at or below that level for nine or more consecutive CGMXCLK. 

V

LVRX

 and V

LVHX

 are determined by the TRPSEL bit in the LVISCR (see 

). LVIPWR and 

LVIRST are in the configuration register (CONFIG). See 

LOW V

DD

LVIRST

V

DD

 > LVItrip = 0

V

DD

 < LVItrip = 1

LVIOUT

LVIPWR

DETECTOR

V

DD

LVI RESET

FROM CONFIG

FROM CONFIG

 V

DD

DIGITAL FILTER

CPU CLOCK

ANLGTRIP

TRPSEL

FROM LVISCR