Fujitsu FR81S Manual Do Utilizador
CHAPTER 39: RAMECC
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAMECC
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
4.9. ECC False Error Generation Address Register
BACKUP-RAM : EFEARA
The bit configuration of the ECC false error generation address register BACKUP-RAM is
shown.
The ECC false error (a pseudo ECC error) generation address register specifies the address where a false
error (a pseudo error) of Backup-RAM is caused.
EFEARA : Address 3006
H
(Access : Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
D10
D9
D8
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit11] Reserved
Always write "0" to these bits.
[bit10 to bit0] D10 to D0 : False error generation address setting bits
These bits set the address where false ECC error (a pseudo ECC error) of Backup-RAM is caused.
ECC error is caused because the write access to this address is generated at EFECRA:FERR ="1", and the
written data contains the error according to the setting of EFECRA by intention.
Note:
The address above is offset in words. Calculate the absolute address by adding the lower 2 bits to the offset
address mentioned above, and then adding the base address of Backup-RAM.
(Absolute address) = (0000_4000
H
) + (Offset indicated by EFEARX + 2b’00)
MB91520 Series
MN705-00010-1v0-E
1307