Fujitsu FR81S Manual Do Utilizador
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
90
4.4.5.
Serial Aid Control Status Register: SACSR
The serial aid control status register (SACSR) allows you to control serial test operations, select how to
activate the serial timer, enable/disable timer interrupts, enable/disable synchronous transmission, set the
division value of the operating clock of the serial timer, and enable/disable the serial timer.
SACSRn(n=0 to 11) : Address Base addr + 08
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
STST
BST
SFD
SFDE
AUTE
TRG1
TRG0
TINT
0
0
0
0
0
0
0
0
Initial value
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
TINTE TSYNE TRGE TDIV3 TDIV2 TDIV1 TDIV0 TMRE
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15] STST: Serial test bit
This bit is used to enable or disable the serial test mode.
When the serial test mode is enabled, SOUT and SIN will be connected inside the multi-function serial
interface, and data to be transmitted from SOUT can be received from SIN without being processed.
When the serial test mode is enabled, the SOUT pin will be fixed to "H", and data input into the SIN pin
will be ignored.
STST
Serial test bit
0
Serial test mode disabled
1
Serial test mode enabled
Note:
This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
[bit14] BST: Baud rate setting flag
This bit is used to indicate that automatic baud rate adjustment was made due to Sync Field reception.
When the fifth falling edge of LIN bus is detected in Sync Field, this bit will be updated.
BST
Baud rate setting flag
0
No automatic baud rate adjustment
1
Automatic baud rate adjustment
Notes:
⋅
If automatic baud rate adjustment is disabled (AUTE="0"), this bit will be fixed to "0".
⋅
When software reset is triggered (SCR:UPCL="1"), this bit will be reset to "0".
⋅
This bit takes effect only when the Sync Field detection flag (SACSR:SFD) is set to "1".
⋅
Writing to this bit has no effect.
[bit13] SFD: Sync Field detection flag
This bit is used to indicate that Sync Field was detected.
When the fifth falling edge of LIN bus is detected in Sync Field, this bit will be set to "1".
When this bit is set to "1" and the Sync Field detection interrupt enable bit (SFDE) is set to "1", a status
interrupt request will be output.
MB91520 Series
MN705-00010-1v0-E
1403